MIL - The University of Tennessee
the university of tennessee machine intelligence lab
  
W. Brad Matthews, Ph.D. (presently with Broadcom, San Jose, CA)
[ cv
  
9631 Cedar Valley Way
Knoxville, TN 37931
Tel: (865) 850-0259
My status
[homepage]
  
Research Fabric on a Chip (FoC) 
  
  Fabric on a Chip (FoC)
  At the heart of any switch or router resides a packet switching fabric subsystem. Coarsely speaking, the latter is in charge of facilitating the effective exchange of packets from the switch input ports to its output ports. Output-queued (OQ) switching architectures, in which arriving packets are predominantly buffered at the output ports, offer highly desirable properties including minimal average packet delay, controllable Quality of Service (QoS) provisioning, and work-conservation. However, as port densities and data rates increase, the inherent characteristics of OQ switches give rise to prohibitive memory requirements that have traditionally rendered infeasible the implementation of large port density OQ systems. Our work focused on novel pipeline memory management architectures, which exploit the unique attributes of FPGAs in order to overcome these limitations. The approach facilitated the future realization of a complete switching fabric on a single chip.
  
Selected Publications
  
[1]     B. Matthews, I. Arel, D. Rose, B. Bollinger, "Multicast and QoS Provisioning in Parallel Shared Memory Switches," IET Proceedings on Communications, September, 2010 [pdf]
[2]     B. Matthews, I. Elhanany, "Hardware Architecture for High-Speed Real-Time Dynamic Programming Applications," IET Proceedings on Computers and Digital Techniques, pp. 164-171, Vol. 2, No. 3, May, 2008 [pdf]
[3]     B. Matthews, I. Elhanany, "A Scalable Memory-Efficient Architecture for Parallel Shared Memory Switches," 2007 IEEE Workshop on High Performance Switching and Routing (HPSR), May, 2007 [pdf]
[4]     B. Matthews, I. Elhanany, V. Tabatabaee, "Accelerated Packet Placement Architecture for Parallel Shared Memory Routers," Proc. of IFIP Networking 2007, May, 2007 [pdf]
[5]     B. Matthews, I. Elhanany, "Switch Fabric on a Reconfigurable Chip using an Accelerated Packet Placement Architecture," 15th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), Feb., 2007, Monterey, CA., February, 2007
[6]     B. Matthews, I. Elhanany, V. Tabatabaee, "Fabric on a Chip: Towards Consolidating Packet Switching Functions on Silicon," 2006 IEEE International Conference on Communications (ICC), Istanbul, Turkey, June, 2006 [pdf]
[7]     B. Matthews, I. Elhanany, "Scalable Hardware Architecture for Real-Time Dynamic Programming Applications," 2006 IEEE Symposium on Field Programmable Custom Computing Machines (FCCM), Napa, CA, April, 2006 [pdf]
[8]     B. Matthews, I. Elhanany, "On the Performance of Output-Queued Cell Switches with Non-Uniformly Distributed Bursty Arrivals," IEE Proceedings on Communications, Vol. 153, No. 2, pp. 201-204, April, 2006 [pdf]
[9]     B. Matthews, i. Elhanany, "A High-Speed Reconfigurable Architecture for Heterogeneous Multimodal Packet Traffic Generation," Proc. IEEE 48th Midwest Symposium on Circuits & Systems (MWSCAS 2005), Cincinnati, Ohio, August, 2005 [pdf]