MIL - The University of Tennessee
the university of tennessee machine intelligence lab
 

Fabric on a Chip

Background and Motivation

Output queued (OQ) switches offer several highly desireable performance characteristics, including minimal average packet delay, controllable Quality of Service (QoS) provisioning, and work-conservation under any admissable traffic conditions. Howver, the memory bandwidth requirements of such systems is O(NR), where N denotes the number of ports the system supports, and R is the line rate for each port. To overcome this impractical requirement, parallel shared memory (PSM) architectures have been proposed as a mechanism to distribute the bandwidth requirements while maintaining the desirable performance aspects of OQ switches. At the core of a PSM switch is the memory management algorithm, which determines for each arriving packet the memory unit in which it will placed. The memory management algorithm presents a significant challenge, mainly dominated by the tradeoff between packet placement complexity and the required number of parallel memories employed.
 
Fig. 1: Consolidation of Multiple Packet Switching Functionalities on a Single Chip
 
 

Research Approach

Our research efforts focus on novel pipeline memory management architectures to identify an optimal, reconfigurable solution to the PSM memory management problem. Fig. 1 depicts the Fabric on a Chip (FoC) paradigm, which advocates the consolidation of many packet switching functions on a single chip, given that the memory management problem is resolved. By achieving such a high level of integration, it is argued that much larger systems can be realized requiring fewer resources while also achieving significant cost and power reduction.[1]
 
 
To establish the validity of this approach, we have presented a pipelined memory management framework [2] that facilitates the realization of a switch fabric on a single chip (see Fig. 2). This was verified through the implementation of an 80 Gbps switch fabric prototype utilizing an Altera Stratix II EPS28S60 FPGA device. The design provided switching functionality for an 8 port switch fabric with line rates operating at 10 Gbps while requiring only 8 on-chip (SRAM) memories. Current efforts are directed towards further reducing the memory requirements as well as the efficient incorporation of quality of service (QoS) provisioning.
Support for this research is partially supported by the Department of Energy (DOE) under research grant DE-FG02-04E25507 and by Altera, Inc.