MIL - The University of Tennessee
the university of tennessee machine intelligence lab
 

High-Performance Packet Switching Architectures

Background and Motivation

Packet switching architectures and scheduling algorithms that offer high-performance for next-generation switches and routers have been the focus of academic and industry studies in recent years. During the next few years, complex scientific experiments are expected to generate several petabytes of data that will be transferred to geographically distributed terascale computing facilities. The evolution of large-scale private scientific networks will yield similar engineering challenges to those facing Internet architects. One of these key challenges is the development of scalable, high-performance switching fabrics that reliably facilitate the exchange of data between the network nodes. These platforms necessitate efficient scheduling and bandwidth management technologies that go well beyond legacy schemes. There is great interest in embracing the challenges of designing, analyzing and demonstrating scalable, high-performance packet-scheduling algorithms, which along with complementing switch architectures, will empower next-generation wireline and wireless networks.
 

Research Approach

Our work focuses on novel architectures and algorithms pertaining to combined input and output queued switch fabric designs. In that context, due to the increase in link rates directly resulting in a decrease of packet duration times, packet-by-packet switching is no longer considered a pragmatic approach for designing scalable systems. To address this challenge, our approach advocates the utilization of frame-based algorithms that relax the timing constraints imposed on scheduling algorithms while retaining key performance characteristics. The algorithms are studied via theoretical stability analysis and evaluated by means of statistical simulations.
This research is partially supported by the Department of Energy (DOE) under research grant DE-FG02-04E25507 .